The present invention relates to a communication apparatus of asynchronous transfer mode (hereafter referred to as ATM) suitable for broad-band communication, and in particular to a CLAD (Cell Assembly and Disassembly) apparatus for generating a frame from fixed length packets (cells) and generating fixed length packets from a frame.
The ATM (Asynchronous Transfer Mode) is a technique capable of sending all of various kinds of information such as speech, video image, and data via the same network. In the ATM system, a communicated data is converted from various forms (e.g. streaming data or various length frames) to fixed-length packets (ATM cells) and the cell is managed as a unit.
For partitioning information frames of various forms to ATM cells, and reconstructing frames from ATM cells, the CLAD (Cell Assembly and Disassembly) function described in "Standard ATM Text" published by ASCII company on March 1995, p. 109 is required. As described in "Standard ATM Text," p. 63, the CLAD has a function of mounting frames or packet data of a higher layer onto cells and reconstructing frames or packets from incoming cells. An example of the CLAD is disclosed in JP-A-7-183887 filed for a Japanese patent application by the present assignee.
The cell disassembly and frame producing function included in the CLAD function is a function of assembling a frame from one or more cells. It becomes necessary to buffer cells in a memory until frame production is completed and the frame is sent to a processor which manages the function of higher layer. This cell buffer memory typically is composed of SRAMs (Static Random Access Memory).
In recent years, enhanced functions are required to the CLAD function. For example, as the Internet spreads, the traffic incorporating IP (Internet Protocol) in the ATM system increases. In the routing of the IP, analysis of data in the IP layer is required. In an ATM system which has IP routing function (IP router) therefore, it is necessary to disassemble an ATM cell once to obtain IP frames, conduct routing decision processing, and then assemble the ATM cells in cases of LAN emulation, IP switching, and the like. In some cases, such an IP router is disposed in a backbone network transmitting data at high bit rate. The cell disassembly and frame assembly apparatus of the CLAD apparatus classifies cells which have arrived for each VC connection, assembles frames, and sends the assembled frames to a processor which manages the function of higher layer. Since frames multiplexed on the transmission channel are sent mixedly in time as ATM cells, the CLAD is required to assemble a plurality of frames at the same time. Since a large number of ATM communication channels are accommodated in a fast ATM switching apparatus, the CLAD function is required to assemble an increased number of frames at the same time. Therefore, it should be considered how to implement a big buffer memory in capacity.
As for implementation of the buffer memory, a method of connecting an external RAM to an LSI including a control circuit and a method of disposing a SRAM within an LSI are typical. If it is attempted to form an ATM CLAD apparatus having a large capacity as in the former method, the access speed to the RAMs and the number of input and output pins of the LSI and the RAM restrict the capacity and speed of CLAD. Furthermore, in the latter case where the LSI incorporates a memory, the area on which the RAM can be mounted is limited and consequently it is difficult to implement a cell buffer with large capacity by using a SRAM. For solving this problem, it is conceivable to embed DRAMs (Dynamic Random Access Memory) having a simple memory structure and a small mounting area as the RAM forming a cell buffer with large capacity instead of the SRAMs.
As described in "VLSI memory" published by Baifukan in November 1994, pp. 101-110, a DRAM is formed by a plurality of banks each having a plurality of memory devices arranged in a matrix form in the column direction and in the row direction. With an address selected by using three parameters, i.e., the column, row, and bank, data writing and reading are executed. Such an access mode that the column is changed with the same bank and row is referred to as column access. Such an access mode that the bank is changed irrespective of the column and row is referred to as bank access. Furthermore, such an access mode that the row is changed with the same bank irrespective of the column is referred to as row access. The DRAM is a memory having such a property (referred to as anisotropy) that a change occurs in the access time and data output time according to each access mode.
To be concrete, in view of access time, fast access is possible in the column access and the bank access. However, the row access requires an access time which is several times as long as that of the column access and the bank access. Furthermore, in the case of the column access, fast data outputting is possible. In the case of the bank access and row access, it takes a time several times as long as that of the column access to output data. Furthermore, in all access modes, the data read time in the read access is longer than the data write time in the write access.
In other words, the DRAM is such a memory that the fastest consecutive access becomes possible when performing the data writing and reading operation by using the consecutive column access, such as the consecutive address read operation and write operation, and fast operation is conducted in this operation mode. In some information processors such as computer systems, a large amount of data, such as picture data and file data of the computer system, are written into a memory in a burst manner (consecutive address write), stored until they are needed, and read out from the memory in a burst manner when needed (consecutive address read). The DRAM is a memory suitable for fast execution of such burst data input and output and storage of data. On the other hand, in such a utilization method that the three access modes occur at random, i.e., addressing in conducting the data read operation and data write operation occurs at random, the latency (access time delay and data output delay) differs because of the anisotropy described above and consequently high throughput cannot be expected. Furthermore, since data disappear when a time has elapsed because of an electric property specific to the structure of the DRAM, it is also necessary to execute data refreshing for providing dedicated timing in order to prevent this.
On the other hand, the CLAD function, categorizes and accommodates the cells which are input from the transmission path periodically, in accordance with the VCI/VPI value. Therefore, the CLAD accesses to the cell buffer at random.
In other words, in the CLAD apparatus, cell inputting and outputting with random addresses are executed nearly continuously in order to assemble a plurality of cells input from each of a plurality of connections. In addition, the random state of the input and output timing and address of the cells input to the CLAD apparatus varies in accordance with the random traffic state of the communication network. Even if it is attempted to define predetermined rules beforehand and exercise control in the CLAD apparatus, such random state varies in accordance with the state of the communication network using a switch.
After the frame assembling finishes, the frame has to be read out. One possible implementation is that higher layer management is performed by MPU (Microprocessor Unit). In such implementation the read timing of MPU is at random. It means that the access wait causes if the MPU tries to read the frame while the CLAD is writing the cell to the buffer. This results in a problem of lowered throughput.
If a DRAM is used in the cell buffer of the CLAD apparatus having the above described properties, the three access modes described above occur at random. Therefore, the anisotropy becomes a bottleneck. If the frame production is not conducted at timing with due regard to the longest access time and the longest data input/output delay of the DRAM, cell loss occurs. If the switching rate is lowered in order to avoid this cell loss, the throughput is lowered. Furthermore, if the data refreshing operation is conducted at appropriate intervals in such a state that the cell inputting and outputting are being executed substantially continuously, the throughput is further limited.
Specifically, the switching rate with due regard to the longest access time and the longest data input and output delay time of the current DRAM is approximately one ten-and-several-th that of the SRAM. Therefore, it is difficult to simply use a DRAM in the CLAD apparatus of the ATM system required to have high throughput.
As one of the ATM switching systems, a shared buffer type switch is known. In this case, ATM cells sent from a plurality of input ports to the switching system in parallel are converted to a time series of ATM cells by a multiplexer, and thereafter temporarily stored in a shared buffer memory. The ATM cells read out from the buffer memory are selectively distributed to one of a plurality of output ports associated with header information (VP/VCI) of each cell, via a demultiplexer.
U.S. Pat. No. 5,099,475 discloses a shared memory type ATM switching system. In this ATM switching system, a buffer memory is formed by eight buffer memory LSIs associated with respective bits of 8 bit parallel format byte of an ATM cell. Each byte of ATM cell data is subjected to bit slice and written into these memory LSIs in parallel.
Furthermore, a literature "32.times.32 Shared Buffer Type ATM system VLSI for B-ISDN," IEEE International Conference on Communications, Jun. 23-26, 1991 discloses configuring the above described bit sliced buffer memory LSIs by using synchronous-clocked static RAMs.